The present invention relates to a digital time base corrector which is applied to form a data lack interval for addition of redundancy data when, for example, a digital video signal is recorded or contrarily to derive a continuous digital video signal by removing a data lack interval.
This invention intends to realize a time base correction by means of a digital variable delay circuit in which a delay amount can be varied for every clock. As one of conventional digital variable delay circuits, there has been known a delay circuit of the type in which: shift registers having eight stages, four stages, two stages, and one stage are cascade connected between its input and output terminals; a multiplexer to select either one of the data transmitted through the shift register and the data transmitted without passing through this shift register is provided at each connecting point between the shift registers; and a desired delay amount among zero stage, one stage, . . . , and fifteen stages can be set by controlling the multiplexers. Such a conventional variable delay circuit cannot change the delay amount for every clock, so that it is improper as a time base corrector for producing or removing an arbitrary data lack interval.
On one hand, as another example of the conventional delay circuits, there has been known a delay circuit of this type in which, for example, three shift registers each having k stages are cascaded connected and either one of total four data of an output of this cascade connection, an input data, an output of the shift register at the first stage, and an output of the second shift register is selected by a multiplexer. This variable delay circuit cannot form a data lack interval of an arbitrary length on one-clock unit basis, so that there is a drawback.
FIG. 1 shows further another example of the conventional variable delay circuits. An input data is supplied to a shift register 1 in which registers R.sub.1, R.sub.2, R.sub.3, . . . , R.sub.n-1, and R.sub.n of n stages are connected in series. n bits which are fetched respectively from between the respective stages of the registers and from an output of the register R.sub.n are supplied to a selector 2. The shift register 1 performs the shifting operation in response to a clock synchronized with the input data. The selector 2 selects one bit from n bits and outputs it. The selection of one bit by the selector 2 is controlled by an output of a decoder 3. Therefore, a desired delay amount can be derived by way of a selecting signal which is supplied to the decoder 3.
The foregoing conventional variable delay circuit has drawbacks such that propagation delay times in the selector 2 and decoder 3 become long with an increase in number n of stages and an arrangement of the selector 2 also becomes complicated. Therefore, in case of a digital video signal whose sampling period is so short as to be 90 nsec, a desired signal cannot be derived in the stable state for every clock.
In addition to this, it is difficult to vary the delay amount to be set for every clock.
Hitherto, the time base corrector has been constituted using a RAM (random access memory) in place of a variable delay circuit. However, to store and read out high speed data such as a digital video signal, it is necessary to use a plurality of, for instance, K RAMs in parallel and thereby to reduce the storing speed into and reading speed from the RAM to 1/K of those in the case where a single RAM is used. In case of producing a data lack interval by making the RAMs operative in parallel and stopping a read counter as described above, there is a problem such that the length of data lack interval can be set only on a K-clock unit basis.